The present invention relates to a method for buffer management and a controller of the same for improving the efficiency of buffer management, and especially to a data accessing method for managing a buffer by a buffer controller.
A buffer is provided for a controller and a connected device for buffering and management while accessing data. Referring to FIG. 1, a general block schematic view of a buffer and a processor is illustrated. As shown in the FIG. 1, a buffer controller 20 is provided between a processor 10 and a buffer memory 30. The buffer memory 30 can be synchronous dynamic random access memory (SDRAM) or static random access memory (SRAM). The buffer controller 20 controls the data accessing between the processor 10 and the buffer memory 30. Referring to FIG. 2, a schematic view of a prior art buffer management by bit mask. As shown in the figure, the buffer controller 20 is installed with a bit masker 202 for recording the use of the segments 30.0001 to 30.2048 in the buffer memory 30, namely the bit masker is installed with 2048 bits corresponding to the segments 30.0001 to 30.2048 in the buffer memory 30. Therefore, as the processor 10 processes data, the system can real-time allocate the required memory for the processor 10 according to the bit mask status of the bit masker 202 from the buffer controller 20. The physical memory size required by the bit masker 202 is very large and thus cost a lot. As a result, it can not match the requirement in the industry.
Another way for managing the buffer is by a linked list. Referring to FIG. 3, a schematic view for the prior art buffer management using a linked list is illustrated. In initialization, as shown in the figure, the segments 30.0001 to 30.2048 in the buffer memory 30 are serially linked. Furthermore, the segment 30.0001 has a tail node pointing to the 30.0002 and the tail of the segment 30,0002 points to the segment 30.0003. The processes repeats continuously until the segment 30.2048 is pointed and linked, while the segment 30.2048 is pointed to null. Null represents an end of the free linked list. The buffer controller 20 is installed with a pointer 204 for recording a first unused segment, i.e. the head of the free linked list. Initially, as the first unused segment has an address 30.0001, the pointer points to the segment 30.0001. If the segment 30.0001 is stored with data, the pointer is necessary to read the tail node of the segment 30.0001 for updating its content and then point to the segment 30.0002. Later, if the content of the segment 30.0001 is processed and the segment 30.0001 needs to be freed back to the free linked list. The buffer controller 20 frees the segment 30.0001 to the head of the free linked list. Namely, the tail node of the segment 30.0001 must be updated to point to the new head of the free segments originally recorded in the pointer 204. Then the pointer 204 points to the segment 30.0001 so as to complete the linkage. Therefore, although it is only purely to assign and free one segment in the buffer memory, it involves a complex hardware operation. Although, applying the linked list can save a lot of bit mask memory and the cost is reduced. The efficiency is low and the loading of the static random access memory is high due to the frequent access. This does not match the requirement of the industry.
Therefore, there is a need for a method for buffer management and a controller of the same to resolve the prior art problems.
Accordingly, the primary object of the present invention is to provide a method for buffer management for improving the efficiency of buffer management and a controller thereof. In the buffer management method, a first control mode is performed, wherein a plurality of bits are used to control a bit mask region of a memory. A second control mode is performed, and a plurality of unused addresses in a link region in the memory is cached. A third control mode is performed, to control a plurality of second unused addresses in the link region by a linked list.
The present invention further provides a controller comprising a plurality of bits for controlling the utilization status of a bit mask region; a plurality of address cache units for caching a plurality of first unused address in the link region; and a pointer for pointing to a head of a linked list in a link region of the memory, and the linked list links a plurality of second unused addresses.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.